The CPUID Explorer:
Part 2: The details
|
|
Home |
 |
Back To Tips Page |
| Back to Part 1 |
|
|
The CPUID Explorer:
|
|
There are no structures defined for this information.
CPUregs regs; GetCPUID(0, ®s); CStringA b((LPCSTR)®s.EBX, 4); CStringA c((LPCSTR)®s.ECX, 4); CStringA d((LPCSTR)®s.EDX, 4); CString CPUTypeName(b + d + c);
EAX (Intel): 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 +--------+----------------+--------+----+----+--------+--------+--------+ |########|Extended family |Extmodel|####|type|familyid| model |stepping| +--------+----------------+--------+----+----+--------+--------+--------+ EAX (AMD): 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 +--------+----------------+--------+----+----+--------+--------+--------+ |########|Extended family |Extmodel|####|####|familyid| model |stepping| +--------+----------------+--------+----+----+--------+--------+--------+
typedef union {
struct { // low order
UINT SteppingID:4; // 3..0
UINT ModelID:4; // 7..4
UINT FamilyID:4; // 11..8
UINT ProcessorType:2; // 13..12
UINT Reserved2:2; // 15..14
UINT ExtendedModel:4; // 19..16
UINT ExtendedFamily:8; // 27..20
UINT Reserved:4; // 31..28
} Intel; // high order
struct { // low order
UINT SteppingID:4; // 3..0
UINT ModelID:4; // 7..4
UINT FamilyID:4; // 11..8
UINT Reserved2:4; // 15..12
UINT ExtendedModel:4; // 19..16
UINT ExtendedFamily:8; // 27..20
UINT Reserved:4; // 31..28
} AMD; // high order
UINT w;
} EAX1b;
CPUregs regs;
GetCPUID(1, regs);
EAX1b EAX;
EAX.w = regs.EAX;
UINT ComputedModel;
if(EAX.bits.FamilyID == 0x06 || EAX.bits.FamilyID == 0x0F)
{ /* extended model */
ComputedModel = EAX.bits.ModelID + (EAX.bits.ExtendedModel << 4);
} /* extended model */
else
{ /* not extended model */
ComputedModel = EAX.bits.ModelID;
} /* not extended model */
//********************************
UINT ComputedFamily;
if(EAX.bits.FamilyID == 0x0F)
{ /* extended family ID */
ComputedFamily = EAX.bits.FamilyID + EAX.bits.ExtendedFamily;
} /* extended family ID */
else
{ /* not extended */
ComputedFamily = EAX.bits.FamilyID;
} /* not extended */
IDS_PROCESSOR_00B "Original OEM processor" IDS_PROCESSOR_01B "Intel Overdrive ® processor" IDS_PROCESSOR_10B "Dual processor" IDS_PROCESSOR_11B "Intel reserved"
31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | Initial APIC ID|LogicalProcessor|CLFLUSHLineSize | Brand Index | +----------------+----------------+----------------+----------------+
typedef union {
struct { // low order
UINT BrandIndex:8;
UINT CLFLUSHLineSize:8;
UINT LogicalProcessors:8;
UINT InitialAPICID:8;
} bits; // high order
UINT w;
} EBX1b;
CPUregs regs; GetCPUID(1, ®s); EBX1b EBX; EBX.w = regs.EBX; UINT ComputedCLFLUSHLineSize = EBX.bits.CLFLUSHLineSize * 8; UINT NumberOfLogicalProcessors = (EBX.bits.LogicalProcessors == 0 ? 1 : EBX.bits.LogicalProcessors);
IDS_BRAND_INDEX_01H "Intel ® Celeron ® processor" IDS_BRAND_INDEX_02H "Intel ® Pentium ® III processor" IDS_BRAND_INDEX_03H "Intel ® Pentium ® III Xeon(tm) processor\nIntel ® Celeron ® processor" IDS_BRAND_INDEX_04H "Intel ® Pentium ® III processor" IDS_BRAND_INDEX_06H "Mobile Intel ® Pentium ® III processor-M" IDS_BRAND_INDEX_07H "Mobile Intel ® Celeron ® processor" IDS_BRAND_INDEX_08H "Intel ® Pentium ® 4 processor" IDS_BRAND_INDEX_09H "Intel ® Pentium ® 4 processor" IDS_BRAND_INDEX_0AH "Intel ® Celeron ® processor" IDS_BRAND_INDEX_0BH "Intel ® Xeon(tm) processor\nIntel ® Xeon(tm) processor MP" IDS_BRAND_INDEX_0CH "Intel ® Xeon(tm) processor MP" IDS_BRAND_INDEX_0EH "Mobile Intel ® Pentium ® 4 processor\nIntel ® Xeon(tm) processor" IDS_BRAND_INDEX_0FH "Mobile Intel ® Celeron ® processor" IDS_BRAND_INDEX_11H "Mobile Genuine Intel ® processor" IDS_BRAND_INDEX_12H "Intel ® Celeron ® M processor" IDS_BRAND_INDEX_13H "Mobile Intel ® Celeron ® processor" IDS_BRAND_INDEX_14H "Intel ® Celeron ® processor" IDS_BRAND_INDEX_15H "Mobile Genuine Intel ® processor" IDS_BRAND_INDEX_16H "Intel ® Pentium ® M processor" IDS_BRAND_INDEX_17H "Mobile Intel ® Celeron ® processor"
Intel 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +------------------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |####################################|CX|##|##|L1|##|T2|ES|##|VM|CP|MW|##|##|S3| +------------------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ AMD 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +------------------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |####################################|CX|##|##|##|##|##|##|##|##|##|##|##|##|S3| +------------------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
CX - CompareAndExchange16B supported L1 - L1 context ID supported T2 - Thermal Monitor 2 supported ES - Enhanced SpeedStep technology VM - VMX technology CP - CPL-qualified debug store MW - MWAIT supported S3 - SSE3 supported
typedef union {
struct { // low order
UINT SSE3:1; // 0
UINT Reserved1:2; // 2..1
UINT MWAIT:1; // 3
UINT CPL:1; // 4
UINT VMX:1; // 5
UINT Reserved2:1; // 6
UINT EST:1; // 7
UINT TM2:1; // 8
UINT Reserved3:1; // 9
UINT L1:1; // 10
UINT Reserved4:1; // 11
UINT Reserved5:1; // 12
UINT CMPXCHG16B:1; // 13
UINT Reserved6:18; // 31..14
} Intel; // high order
struct { // low order
UINT SSE3:1; // 0
UINT Reserved1:3; // 3..1
UINT Reserved2:4; // 7..4
UINT Reserved3:4; // 11..8
UINT Reserved5:1; // 12
UINT CMPXCHG16B:1; // 13
UINT reserved6:18; // 14..31
} AMD; // high order
UINT w;
} ECX1b;
CPUregs regs; GetCPUID(1, ®s); ECX1b ECX; ECX.w = regs.ECX;
EDX: Extended feature bits (Intel) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |PB|##|TM|HT|SS|S2|S1|FX|MM|AC|DS|##|CF|PN|P3|PT|CM|MC|PG|MT|SE|##|AP|CX|ME|PA|MS|TS|PS|DE|V8|FP| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ EDX: Extended feature bits (AMD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |##|##|##|HT|##|S2|S1|FX|MM|##|##|##|CF|##|P3|PT|CM|MC|PG|MT|SE|##|AP|CX|ME|PA|MS|TS|PS|DE|V8|FP| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ PB - Pending Break Enable TM - Thermal Monitor HT - Hyperthreading SS - Self-Snoop S2 - SSE2 extensions S1 - SSE extensions MM - MMX AC - ACPI DS - Debug Store CF - CFLUSH instruction PN - Processor serial number P3 - PSE36 Size extensions PT - Page attribute table CM - CMOV: Conditional move/compare instruction MC - Machine Check Architecture PG - Global PTE bit MT - Memory Type Range Registers SE - SYSENTER/SYSEXIT AP - APIC on-chip CX - CMXCHG8B ME - Machine Check Exception PA - Physical Address Extension MS - RDMSR/WRMSR support TS - TimeStamp Counter PS - Page Size extensions DE - Debugging extensions V8 - Virtual 8086 extensions FP - FPU87 on chip
typedef union {
struct { // low order
UINT FPU:1; // 0
UINT VME:1; // 1
UINT DE:1; // 2
UINT PSE:1; // 3
UINT MSR:1; // 4
UINT TSC:1; // 5
UINT PAE:1; // 6
UINT MCE:1; // 7
UINT CX8:1; // 8
UINT APIC:1; // 9
UINT reserved1:1; // 10
UINT SEP:1; // 11
UINT MTRR:1; // 12
UINT PGE:1; // 13
UINT MCA:1; // 14
UINT CMOV:1; // 15
UINT PAT:1; // 16
UINT PSE36:1; // 17
UINT PSN:1; // 18
UINT CFLSH:1; // 19
UINT Reserved2:1; // 20
UINT DS:1; // 21
UINT ACPI:1; // 22
UINT MMX:1; // 23
UINT FXSR:1; // 24
UINT SSE:1; // 25
UINT SSE2:1; // 26
UINT SS:1; // 27
UINT HTT:1; // 28
UINT TM:1; // 29
UINT Reserved3:1; // 30
UINT PBE:1; // 31
} Intel; // high order
struct { // low order
UINT FPU:1; // 0
UINT VME:1; // 1
UINT DE:1; // 2
UINT PSE:1; // 3
UINT MSR:1; // 4
UINT TSC:1; // 5
UINT PAE:1; // 6
UINT MCE:1; // 7
UINT CX8:1; // 8
UINT APIC:1; // 9
UINT Reserved1:1; // 10
UINT SEP:1; // 11
UINT MTRR:1; // 12
UINT PGE:1; // 13
UINT MCA:1; // 14
UINT CMOV:1; // 15
UINT PAT:1; // 16
UINT PSE36:1; // 17
UINT Reserved5:1; // 18
UINT CFLSH:1; // 19
UINT Reserved2:3; // 22..20
UINT MMX:1; // 23
UINT FXSR:1; // 24
UINT SSE:1; // 25
UINT SSE2:1; // 26
UINT Reserved4:1; // 27
UINT HTT:1; // 28
UINT Reserved3:3; // 31..29
} AMD; // high order
UINT w;
} EDX1b;
CPUregs regs; GetCPUID(1, ®s); EDX1b EDX; EDX.w = regs.EDX;
The display here is not graphical, but rather tabular, which captures better the notion that the set of attributes is an unordered set of values found in the four regsiters.
This display is not supported for the AMD architecture. Cache and TLB information is available using CPUID(0x80000006):ECX.
EAX:
31 0 +--------+--------+--------+--------+ |0 desc | desc | desc | count | +--------+--------+--------+--------+
EBX:
31 0 +--------+--------+--------+--------+ |0 desc | desc | desc | desc | +--------+--------+--------+--------+ |1#######|########|########|########| +--------+--------+--------+--------+
ECX:
31 0 +--------+--------+--------+--------+ |0 desc | desc | desc | desc | +--------+--------+--------+--------+ |1#######|########|########|########| +--------+--------+--------+--------+
EDX:
31 0 +--------+--------+--------+--------+ |0 desc | desc | desc | desc | +--------+--------+--------+--------+ |1#######|########|########|########| +--------+--------+--------+--------+
If the high-order bit of the register is 0, then each byte in the register contains a valid cache/TLB descriptor. If the high-order bit of the register is 1, then each byte in the register is reserved and has no meaning. I have not run across any machine that has a count value of > 1.
typedef union {
CPUregs regs;
BYTE descriptors[16];
} EREGS2;
EREGS2 ER;
CPUID(2, &ER.regs);
if(ER.descriptors[0] != 0x00)
{ /* valid descriptors */
for(int i = 1; i < sizeof(ER.regs.descriptors); i++)
{ /* decode each descriptor */
if((i & 0x3 == 0) && (ER.descriptors[i] & 0x80))
{ /* invalid descriptors */
i += 3;
continue;
} /* invalid descriptors */
... decode ER.descriptors[i]
} /* decode each descriptor */
} /* valid descriptors */
The above code assumes that the low-order byte of EAX is 1. A more complex loop would be required to handle other cases; note that the value in AL appears to be valid in subsequent operations. The documentation is unclear on this fact, however.
The special test for descriptors[0] == 0 is required because the AMD processors return all zeroes, and do not set any high-order bit to 1.
IDS_CTLB_00H "Null descriptor" IDS_CTLB_01H "Instruction TLB: 4K pages, 4-way set associative, 32 entries\nI 4Kx4wx32" IDS_CTLB_02H "Instruction TLB: 4K pages, 4-way set associative, 2 entries\nI 4Kx4wx2" IDS_CTLB_03H "Data TLB: 4K pages, 4-way set associative, 64 entries\nD 4Kx4wx64" IDS_CTLB_04H "Data TLB: 4M pages, 4-way set associative, 8 entries\nD 4Mx4wx8" IDS_CTLB_05H "Data TLB: 4M pages, 4-way set associative, 8 entries\n4Mx4wx8" IDS_CTLB_06H "1st-level instruction cache: 8K, 4-way set associative, 32 byte line size\nI 8Kx4wx32" IDS_CTLB_08H "1st-level instruction cache: 16K, 4-way set associative, 32 byte line size\nI 16Kx4wx32" IDS_CTLB_0AH "1st-level data cache: 8K, 2-way set associative, 32 byte line size\nD 8Kx2wx32" IDS_CTLB_0CH "1st-level data cache: 16K, 4-way set associative, 32 byte line size\nD 16Kx4wx32" IDS_CTLB_22H "3rd-level cache: 512K, 4-way set associative, 64-byte line size, 2 lines per sector\n512Kx4wx64" IDS_CTLB_23H "3rd-level cache; 1M, 8-way set associative, 64 byte line size, 2 lines per sector\n1Mx8wx64" IDS_CTLB_25H "3rd-level cache: 2M, 8-way set associative, 64 byte line size, 2 lines per sector\n2Mx8wx64" IDS_CTLB_29H "3rd-level cache: 4M, 8-way set associative, 64 byte line size, 2 lines per sector\n4Mx8wx64" IDS_CTLB_2CH "1st-level data cache: 32K, 8-way asociative, 64 byte line size\nD 32Kx8wx64" IDS_CTLB_30H "1st-level instruction cache: 32K, 8-way set associative, 64 byte line size\nI 32Kx8wx64" IDS_CTLB_40H "No 2nd-level cache, or, if processor contains a valid 2nd-level cache, no 3rd-level cache" IDS_CTLB_41H "2nd-level cache: 128K, 4-way set associative, 32 byte line size\n128Kx4wx32" IDS_CTLB_42H "2nd-level cache: 256K, 4-way set associative, 32 byte line size\n256Kx4wx32" IDS_CTLB_43H "2nd-level cache: 512K, 4-way set associative, 32 byte line size\n512Kx4wx32" IDS_CTLB_44H "2nd-level cache: 1M, 4-way set associative, 32 byte line size\n1Mx4wx32" IDS_CTLB_45H "2nd-level cache: 2M, 4-way set associative, 32 byte line size\n2Mx4wx32" IDS_CTLB_46H "3rd-level cache: 4M, 4-way set associative, 64 byte line size\n4Mx4wx64" IDS_CTLB_47H "3rd-level cache, 8M, 8-way set associative, 64 byte line size\n8Mx8wx64" IDS_CTLB_49H "2nd-level cache: 4M, 16-way set associative, 64 byte line size\n4Mx16wx64" IDS_CTLB_50H "Instruction TLB: 4K and 2M or 4M pages, 64 entries\nI 4K+2M/4Mx64" IDS_CTLB_51H "Instruction TLB: 4K and 2M or 4M pages, 128 entries\nI 4K+2M/4Mx128" IDS_CTLB_52H "Instruction TLB: 4K and 2M or 4M pages, 256 entries\nI 4K+2M/4Mx256" IDS_CTLB_56H "Data TLB0: 4M pages, 4-way set associative, 16 entries\nD 4Mx4wx16" IDS_CTLB_57H "Data TLB0: 4K pages, 4-way set associative, 16 entries\nD 4Kx4wx16" IDS_CTLB_5BH "Data TLB: 4K and 4M pages, 64 entries\nD 4K+4Mx64" IDS_CTLB_5CH "Data TLB: 4K and 4M pages, 128 entries\nD 4K+4Mx128" IDS_CTLB_5DH "Data TLB: 4K and 4M pages, 256 entries\nD 4K+4Mx254" IDS_CTLB_60H "1st-level data cache: 16K, 8-way set associative, 64 byte line size\n16Kx8x64" IDS_CTLB_66H "1st-level data cache: 8K, 4-way set associative, 64 byte line size\n8Kx4wx64" IDS_CTLB_67H "1st-level data cache: 16K, 4-way set associative, 64 byte line size\n16Kx4wx64" IDS_CTLB_68H "1st-level data cache: 32K, 4-way set associative, 64 byte line size\n32Kx4wx64" IDS_CLTB_70H "Trace cache: 12K-uOp, 8-way set associative\nTr 12Kx8w" IDS_CTLB_71H "Trace cache: 16K-uOp, 8-way set associative\nTr 16Kx8w" IDS_CTLB_72H "Trace cache: 32K-uOp, 8-way set associative\nTr 32Kx8w" IDS_CTLB_78H "2nd-level cache: 128K, 8-way set associative, 64 byte line size\n128Kx8wx64" IDS_CTLB_79H "2nd-level cache: 128K, 8-way set associative, 64 byte line size, 2 lines per sector\n128Kx8wx64" IDS_CTLB_7AH "2nd-level cache: 256K, 8-way set associative, 64 byte line size, 2 lines per sector\n256Kx8wx64" IDS_CTLB_7BH "2nd-level cache: 512K, 8-way set associative, 64 byte line size, 2 lines per sector\n512Kx8wx64" IDS_CTLB_7CH "2nd-level cache: 1M, 8-way set associative, 64 byte line size, 2 lines per sector\n1Mx8wx64" IDS_CTLB_7DH "2nd-level cache: 2M, 8-way set associative, 64 byte line size\n2Mx82x64" IDS_CTLB_7FH "2nd-level cache: 512K, 2-way set associative, 64 byte line size\n512Kx2wx64" IDS_CTLB_82H "2nd-level cache: 256K, 8-way set associative, 32 byte line size\n256Kx8wx32" IDS_CTLB_83H "2nd-level cache: 512K, 8-way set associative, 32 byte line size\n512Kx8wx32" IDS_CTLB_84H "2nd-level cache: 1M, 8-way set associative, 32 byte line size\n1Mx8wx32" IDS_CTLB_85H "2nd-level cache: 2M, 8-way set associative, 32 byte line size\n2Mx8wx32" IDS_CTLB_86H "2nd-level cache: 512K, 4-way set associative, 64 byte line size\n512Kx4wx64" IDS_CTLB_87H "2nd-level cache: 1M, 8-way set associative, 64 byte line size\n1Mx8wx64" IDS_CTLB_B0H "Instruction TLB: 4K pages, 4-way set associative, 128 entries\nI 4Kx4x128" IDS_CTLB_B3H "Data TLB: 4K pages, 4-way set associative, 128 entries\nD 4Kx4wx128" IDS_CTLB_B4H "Data TLB1: 4K pages, 4-way set associative, 256 entries\nD 4Kx4wx256" IDS_CTLB_F0H "64-byte prefetching" IDS_CTLB_F1H "128-byte prefetching"
Note that this page is only displayed in debug mode, unless the processor has a processor serial number capability. No CPU since the Pentium III has had this capability, and therefore this page is not normally displayed. This page will not display in release mode if CPUID(0).EAX < 3.
This display is not supported for AMD platforms.
CPUregs regs;
GetCPUID(1, ®s);
EDX1b EDX;
EDX.w = regs.EDX;
if(regs.EAX >= 3 && EDX.bits.PSN)
{ /* has processor serial number */
GetCPUID(3, ®s);
LARGE_INTEGER serial;
serial.LowPart = regs.ECX;
serial.HighPart = regs.EDX;
... use serial.QuadPart here
} /* has processor serial number */
Note that each cache line display for each value of n is essentially identical. However, if the cache type is undefined, then that information is not displayed. In debug mode, cache line pages 1..6 will always be displayed. The number of caches reported is currently fixed at compile time and limited to at most 6 caches. More can be added by adding more pages. In release mode, these pages will not be displayed if CPUID(0).EAX < 4.
This display is not supported for AMD platforms.
EAX:
31 26 25 14 13 10 9 8 7 5 4 0 +------------+------------------------+--------+--+--+------+----------+ | cores/pkg | threads sharing cache-1|########|FA|SI|Level | Type | +------------+------------------------+--------+--+--+------+----------+ FA - Fully associative | SI - Self-initializing | | +---------------------------------------------------------------+ | 00H - no more cache information 01H - Data cache 02H - Instruction cache 03H - Unified (data + instruction) cache
EBX:
31 22 21 12 11 0 +--------------------+--------------------+------------------------+ | associativity - 1 | line partitions - 1|Coherency line size - 1 | +--------------------+--------------------+------------------------+
ECX:
31 0 +------------------------------------------------------------------+ | Number of sets -1 | +------------------------------------------------------------------+
EDX: Reserved
typedef union {
struct { // low order
UINT CacheType:5; // 4..0
UINT CacheLevel:3; // 7..5
UINT SelfInitializing:1; // 8
UINT FullyAssociative:1; // 9
UINT Reserved:4; // 13..10
UINT ThreadsSharing:12; // 25..14
UINT CoresPerPackage:6; // 31..26
} bits; // high order
UINT w;
} EAX4b;
typedef union {
struct { // low order
UINT SystemCoherencyLineSize:12; // 11..0
UINT PhysicalLinePartitions:10; // 21..12
UINT WaysOfAssociativity:10; // 32..22
} bits; // high order
UINT w;
} EBX4b;
for(UINT i = 0; i < 256; i++)
{ /* examine each level */
CPUregs regs;
regs.ECX = i; // Note that ECX must be set before doing the call!
GetCPUID(4, ®s);
EAX4b EAX;
EAX.w = regs.EAX;if(EAX.bits.CacheType == 0) break; // no more cache information available UINT ActualThreadsSharingCache = EAX.ThreadsSharing + 1; UINT ActualCoresPerPackage = EAX.CoresPerPackage + 1; EBX4b EBX; EBX.w = regs.EBX; UINT ActualSystemCoherencyLineSize = EBX.SystemCoherencyLineSize + 1; UINT ActualPhysicalLinePartitions = EBX.PhysicalLinePartitions + 1; UINT ActualNumberOfSets = regs.ECX + 1; ... use cache information here } /* examine each level */
IDS_CACHE_TYPE_01 "Data cache" IDS_CACHE_TYPE_02 "Instruction cache" IDS_CACHE_TYPE_03 "Unified (data + instruction) cache"
This page will not be displayed in release mode if CPUID(0).EAX < 5.
Note: This screen shot is obsolete, and was made on an older machine not currently available to the author. The mechanism for writing configurations was added after this screen shot was taken.
EAX:
31 16 15 0 +--------------------------------+--------------------------------+ |################################| Smallest monitor line size | +--------------------------------+--------------------------------+
EBX:
31 16 15 0 +--------------------------------+--------------------------------+ |################################| Largest monitor line size | +--------------------------------+--------------------------------+
ECX: 31 2 1 0 +----------------------------------------------------------------+--+--+ |################################################################|IB|ES| +----------------------------------------------------------------+--+--+ ES: Enumeration supported beyond EAX/EBX IB: Interrupts supported as break events EDX: 31 20 19 16 15 12 11 8 7 4 3 0 +------------------------+--------+--------+--------+--------+--------+ |########################| C4 | C3 | C2 | C1 | C0 | +------------------------+--------+--------+--------+--------+--------+ Number of C0 sub C states supported using MWAIT Number of C1 sub C states supported using MWAIT Number of C2 sub C states supported using MWAIT Number of C3 sub C states supported using MWAIT Number of C4 sub C states supported using MWAIT
typedef union {
struct { // low order
UINT SmallestMonitorLineSize:16; // 15..0
UINT Reserved2:16; // 31..16
} bits; // high order
UINT w;
} EAX5b;
typedef union {
struct { // low order
UINT LargestMonitorLineSize:16; // 15..0
UINT Reserved1:16; // 31..16
} bits; // high order
UINT w;
} EBX5b;
typedef union {
struct { // low order
UINT MWAITEnumerationSupported:1; // 0
UINT InterruptsAsBreakEvents:1; // 1
UINT Reserved3:30; // 31..2
} bits;
UINT w;
} ECX5b;
typedef union {
struct { // low order
UINT C0:4; // 0..3
UINT C1:4; // 4..7
UINT C2:4; // 8..11
UINT C3:4; // 15..12
UINT C4:4; // 19..16
UINT Reserved4:12; // 31..29
} bits; // high order
UINT w;
} EDX5b;
(No screen shot available)
EAX: 31 1 0 +--------------------------------------------------------------+--+ |##############################################################|DS| +--------------------------------------------------------------+--+ DS - Digital Temperature Sensor supporte EBX: 31 1 0 +--------------------------------------------------------+--------+ |########################################################| thcnt | +--------------------------------------------------------+--------+ thcnt - Number of interrupt thresholds in temperature sensor ECX: 31 1 0 +--------------------------------------------------------------+--+ |##############################################################|EC| +--------------------------------------------------------------+--+ EC - ECNT/MCNT supported
typedef union {
struct { // low order
UINT SensorSupported:1; // 0
UINT Reserved1:31; // 31..1
} bits; // high order
UINT w;
} EAX6b;
typedef union {
struct { // low order
UINT InterruptThresholds:4;// 3..0
UINT Reserved2:26; // 31..4
} bits; // high order
UINT w;
} EBX6b;
typedef union {
struct { // low order
UINT ACNT_MCNT:1; // 0
UINT Reserved3:31; // 31..1
} bits; // high order
UINT w;
} ECX6b;
(no screen shot available)
EAX: 31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | EBX vector len | GP bit width | counters | version ID | +----------------+----------------+----------------+----------------+ EBX: 31 7 6 5 4 3 2 1 0 +----------------------------------------------+--+--+--+--+--+--+--+ |##############################################|BM|BI|CM|CR|RC|IR|CC| +----------------------------------------------+--+--+--+--+--+--+--+ CC - Core cycle event not available IR - Instruction retired event not available RC - Reference Cycles event not available CR - Last level cache reference event not available CM - Last-level cache-misses event not available BI - Branch Instruction retired event not available BM - Branch Mispredict retired event not available ECX: Reserved EDX: 31 13 12 5 4 0 +-------------------------------------+------------------+----------+ |#####################################| width of counters| counters | +-------------------------------------+------------------+----------+
typedef union {
struct { // low order
UINT VersionID:8; // 7..0
UINT GPCounters:8; // 15..8
UINT GPCounterWidth:8; // 23..16
UINT EBXVectorLength:8; // 31..24
} bits; // high order
UINT w;
} EAX10b;
typedef union {
struct { // low order
UINT CoreCycleNA:1; // 0
UINT InstructionRetiredNA:1; // 1
UINT ReferenceCyclesNA:1; // 2
UINT CacheReferenceNA:1; // 3
UINT CacheMissNA:1; // 4
UINT BranchRetiredNA:1; // 5
UINT BranchMispredictNA:1; // 6
UINT Reserved1:25; // 31..7
} bits; // high order
UINT w;
} EBX10b;
typedef union {
struct { // low order
UINT FixedFunctionCounters:5; // 4..0
UINT CounterBitWidth:8; // 12..5
UINT Reserved2:19; // 31..13
} bits; // high order
UINT w;
} EDX10b;
EAX: The highest vale of extended CPUID request permitted
EBX: Reserved
ECX: Reserved
EDX: Reserved
CPUregs regs; CPUID(0x80000001, ®s);
The AMD registers are too detailed to show on one page; see CPUID(0x80000001):EAX, CPUID(0x80000001):EBX, CPUID(x80000001):ECX and CPUID(0x80000001):EDX.
EAX (Intel):
Extended Processor Signature and Feature Bits +----------------------------------------------------------------+ |????????????????????????????????????????????????????????????????| +----------------------------------------------------------------+
Note that the Intel documentation does not currently describe the format of the contents of the EAX register upon return.
EBX (Intel): Reserved
ECX: Intel 31 1 0 +--------------------------------------------------------------+--+ |##############################################################|LS| +--------------------------------------------------------------+--+ LS- LAHF/SAHF Available (64 bit) ECX: AMD 31 4 3 2 1 0 +--------------------------------------------------+--+--+--+--+--+ |##################################################|AM|##|SV|CL|LS| +--------------------------------------------------+--+--+--+--+--+ CL - CmpLegacy - Core Multiprocessor Legacy mode SV - SVM - Secure Virtual Machine AM - AltMovCR8 - LOCK MOV CR0 == MOV CR8
EDX: (Intel) 31 30 29 28 21 20 19 12 11 10 0 +-----+--+-----------------------+--+-----------------------+--+--------------------------------+ |#####|EM|#######################|ED|#######################|SY|################################| +-----+--+-----------------------+--+-----------------------+--+--------------------------------+ EM - EMT64 available ED - Execute Disable available SY - SYSCALL/SYSRET available (64-bit) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+-----+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |3D|3X|LM|##|RD|##|FF|FX|MM|MX|##|ED|#####|P3|PT|CM|MC|PG|MT|SE|##|AP|CX|ME|PA|MS|TS|PS|DE|V8|FP| +--+--+--+--+--+--+--+--+--+--+--+--+-----+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 3D - 3DNow!(tm) support 3X - 3DNow!(tm) extensions LM - Long mode RD - RSTSCP FF - FFXSR FX - FXSR MM - MMX instructions MX - MMX Extensions NX - No Execute (Execute Disabled) P3 - PSE36 extensions PT - Page attribute table CM - CMOV: Conditional move/compare instruction MC - Machine Check Architecture PG - Global PTE bit MT - Memory Type Range Registers SE - SYSENTER/SYSEXIT AP - APIC on-chip CX - CMXCHG8B ME - Machine Check Exception PA - Physical Address Extension MS - RDMSR/WRMSR support TS - TimeStamp Counter PS - Page Size extensions DE - Debugging extensions V8 - Virtual 8086 extensions FP - FPU87 on chip
typedef union {
struct { // low order
UINT LAHF_SAHF:1; // 0
UINT Reserved5:31; // 31..1
} Intel; // high order
struct { // low order
UINT LAHF_SAHF:1; // 0
UINT CmpLegacy:1; // 1
UINT SVM:1; // 2
UINT Reserved6:1; // 3
UINT AltMovCr8:1; // 4
UINT Reserved5:26; // 31..5
} AMD; // high order
UINT w;
} ECX1x;
typedef union {
struct { // low order
UINT Reserved1:11; // 0..10
UINT SYSCALL_SYSRET:1; // 11
UINT Reserved2:8; // 19..12
UINT ExecuteDisable:1; // 20
UINT Reserved3:8; // 28..21
UINT EMT64T:1; // 29
UINT Reserved4:2; // 30..31
} Intel; // high order
struct { // low order
UINT FPU:1; // 0
UINT VME:1; // 1
UINT DE:1; // 2
UINT PSE:1; // 3
UINT TSC:1; // 4
UINT MSR:1; // 5
UINT PAE:1; // 6
UINT MCE:1; // 7
UINT CMPXCHG8B:1; // 8
UINT APIC:1; // 9
UINT Reserved1:1; // 10
UINT SYSCALL_SYSRET:1; // 11
UINT MTRR:1; // 12
UINT PGE:1; // 13
UINT MCA:1; // 14
UINT CMOV:1; // 15
UINT PAT:1; // 16
UINT PSE36:1; // 17
UINT Reserved2:2; // 19..18
UINT ExecuteDisable:1; // 20
UINT Reserved3:1; // 21
UINT MMXExt:1; // 22
UINT MMX:1; // 23
UINT FXSR:1; // 24
UINT FFXSR:1; // 25
UINT Reserved4:1; // 26
UINT RDTSCP:1; // 27
UINT Reserved5:1; // 28
UINT LM:1; // 29
UINT ThreeDNowExt:1; // 30
UINT ThreeDNow:1; // 31
} AMD; // high order
UINT w;
} EDX1x;
The display for AMD platforms is similar to the CPUID(0) display
This uses the same structure as CPUID(1):EAX.
The same as CPUID(1):EAX
EBX: (AMD) 31 16 15 0 +------------------------------+--------------------------------+ |##############################| BrandID | +------------------------------+--------------------------------+
typedef union {
struct { // low order
UINT Reserved; // 31..0
} Intel; // high order
struct { // low order
UINT BrandId:16; // 15..0
UINT Reserved:16; // 31..16
} AMD;
UINT w;
} EBX1x;
typedef union {
struct { // low order
UINT LAHF_SAHF:1; // 0
UINT Reserved5:31; // 31..1
} Intel; // high order
struct { // low order
UINT LAHF_SAHF:1; // 0
UINT CmpLegacy:1; // 1
UINT SVM:1; // 2
UINT Reserved6:1; // 3
UINT AltMovCr8:1; // 4
UINT Reserved5:26; // 31..5
} AMD; // high order
UINT w;
} ECX1x;
typedef union {
struct { // low order
UINT Reserved1:11; // 0..10
UINT SYSCALL_SYSRET:1; // 11
UINT Reserved2:8; // 19..12
UINT ExecuteDisable:1; // 20
UINT Reserved3:8; // 28..21
UINT EMT64T:1; // 29
UINT Reserved4:2; // 30..31
} Intel; // high order
struct { // low order
UINT FPU:1; // 0
UINT VME:1; // 1
UINT DE:1; // 2
UINT PSE:1; // 3
UINT TSC:1; // 4
UINT MSR:1; // 5
UINT PAE:1; // 6
UINT MCE:1; // 7
UINT CMPXCHG8B:1; // 8
UINT APIC:1; // 9
UINT Reserved1:1; // 10
UINT SYSCALL_SYSRET:1; // 11
UINT MTRR:1; // 12
UINT PGE:1; // 13
UINT MCA:1; // 14
UINT CMOV:1; // 15
UINT PAT:1; // 16
UINT PSE36:1; // 17
UINT Reserved2:2; // 19..18
UINT ExecuteDisable:1; // 20
UINT Reserved3:1; // 21
UINT MMXExt:1; // 22
UINT MMX:1; // 23
UINT FXSR:1; // 24
UINT FFXSR:1; // 25
UINT Reserved4:1; // 26
UINT RDTSCP:1; // 27
UINT Reserved5:1; // 28
UINT LM:1; // 29
UINT ThreeDNowExt:1; // 30
UINT ThreeDNow:1; // 31
} AMD; // high order
UINT w;
} EDX1x;
The display is essentially identical for all pages, so page 0x8000004 is shown here because it illustrates a useful factoid.
The processor brand string is a 48-character (8-bit ANSI) string terminated by a 0 character. In this page, the values seen in the registers are
EAX: 0x7365636f 'seco' EBX: 0x20726f73 ' ros' ECX: 0x30312e31 '01.1' EDX: 0x007a4847 '\0zHG'
The key here is that an x86 is a "little-endian" machine, that is,
when addressing a multibyte value, the address specified is the address of the
low-order byte and increasing addresses in memory represent successively
higher-order bytes. Thus a chacter sequence "1234" is represented as the bytes
in memory
+--+--+--+--+ |31|32|33|34| +--+--+--+--+
This means that if the value is treated as an integer, it is see as the integer value
0x34333231
CPUregs regs; CStringA BrandName;
for(UINT i = 0x80000002; i <= 0x80000004; i++)
{ /* get strings */
GetCPUID(i, ®s);
CStringA a((LPCSTR)®s.EAX, 4);
CStringA b((LPCSTR)®s.EBX, 4);
CStringA c((LPCSTR)®s.ECX, 4);
CStringA d((LPCSTR)®s.EDX, 4);
BrandName += a + b + c + d;
} /* get strings */LPCSTR p = BrandName.GetBuffer(); BrandName.ReleaseBuffer();
A trick in the above code is to deal with the \0 byte which has become part of the string. By doing the GetBuffer and ReleaseBuffer, the length of the string is recomputed and the terminal \0 byte is no longer considered part of the string. This is an MFC programming trick.
This page will not be displayed in release mode if CPUID(0x80000000).EAX < 0x800000005.
All values are reserved
Intel: EAX: Reserved EBX: Reserved ECX: Reserved EDX: Reserved AMD: EAX: 31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | D 2M+4M assoc | D 2M+4M count | I 2M+4M assoc | I 2M+4M count | +----------------+----------------+----------------+----------------+ EBX: 31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | D 4K assoc | D 4K count | I 4K assoc | I 4K count | +----------------+----------------+----------------+----------------+ ECX: 31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | D L1 size (KB) | D L1 assoc | D L1 lines/tag | D L1 line size | +----------------+----------------+----------------+----------------+ EDX: 31 24 23 16 15 8 7 0 +----------------+----------------+----------------+----------------+ | I L1 size (KB) | I L1 assoc | I L1 lines/tag | I L1 line size | +----------------+----------------+----------------+----------------+ | 00 reserved 01 direct mapped 02..FE n-way mapping FF fully associative
typedef union { // 2M+4M page TLB info
struct { // low order
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT InstCount:8; // 7..0
UINT InstAssoc:8; // 15..8
UINT DataCount:8; // 23..16
UINT DataAssoc:8; // 31..24
} AMD;
UINT w;
} EAX5x;
typedef union { // 4K page TLB info
struct { // low order
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT InstCount:8; // 7..0
UINT InstAssoc:8; // 15..8
UINT DataCount:8; // 23..16
UINT DataAssoc:8; // 31..24
} AMD;
UINT w;
} EBX5x;
typedef union { // L1 data cache info
struct { // low order
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT LineSize:8; // 7..0
UINT LinesPerTag:8; // 15..8
UINT Associativity:8;// 23..16
UINT CacheSize:8; // 31..24
} AMD;
UINT w;
} ECX5x;
typedef union { // L1 instruction cache info
struct { // low order
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT LineSize:8; // 7..0
UINT LinesPerTag:8; // 15..8
UINT Associativity:8;// 23..16
UINT CacheSize:8; // 31..24
} AMD;
UINT w;
} EDX5x;
See CPUID(0x80000006):EAX, CPUID(0x8000006):EBX and CPUID(0x80000006):ECX for details
This page is not displayed in a release build unless CPUID(0x80000000).EAX >= 0x80000006.
Intel:
EAX: Reserved EBX: ReservedEDX: Reserved
ECX:
31 16 15 12 11 8 7 0 +------------------------------+--------+--------+----------------+ | Cache size in 1K units |L2 Assoc|########| CacheLineSize | +------------------------------+--------+--------+----------------+ | | 00H Disabled 01H Direct mapped 02H 2-way associative 04H 4-way associative 06H 8-way associative 08H 16-way associative 0FH Fully associative
AMD:
EAX: L2 TLB parameters, 2M/4M pages 31 28 27 16 15 12 11 0 +--------+------------------------+--------+-------------------------+ |D assoc | D size |I assoc | I size | +--------+------------------------+--------+-------------------------+ EBX: L2 TLB parameters, 4K pages 31 28 27 16 15 12 11 0 +--------+------------------------+--------+-------------------------+ |D assoc | D size |I assoc | I size | +--------+------------------------+--------+-------------------------+ ECX: L2 cache parameters 31 16 15 12 11 8 7 0 +---------------------------------+--------+--------+----------------+ | Cache size in 1K units |L2 Assoc| LPT | CacheLineSize | +---------------------------------+--------+--------+----------------+ | | IDS_L2_ASSOCIATIVITY_00H "Disabled" IDS_L2_ASSOCIATIVITY_01H "Direct mapped" IDS_L2_ASSOCIATIVITY_02H "2-way associative" IDS_L2_ASSOCIATIVITY_04H "4-way associative" IDS_L2_ASSOCIATIVITY_06H "8-way associative" IDS_L2_ASSOCIATIVITY_08H "16-way associative" IDS_L2_ASSOCIATIVITY_0FH "Fully associative" LPT - Lines Per Tag EDX: Reserved
typedef union
struct { // low order
UINT LineSize:8; // 7..0
UINT Reserved1:4; // 11..8
UINT Associativity:4; // 15..12
UINT CacheSize:16; // 31..16
} Intel; // high order
struct { // low order
UINT LineSize:8; // 7..0
UINT LinesPerTag:4; // 11.8
UINT Associativity:4; // 15..12
UINT CacheSize:16; // 31..16
} AMD; // high order
UINT w;
} ECX6x;
IDS_L2_ASSOCIATIVITY_00H "Disabled" IDS_L2_ASSOCIATIVITY_01H "Direct mapped" IDS_L2_ASSOCIATIVITY_02H "2-way associative" IDS_L2_ASSOCIATIVITY_04H "4-way associative" IDS_L2_ASSOCIATIVITY_06H "8-way associative" IDS_L2_ASSOCIATIVITY_08H "16-way associative" IDS_L2_ASSOCIATIVITY_0FH "Fully associative"
CPUregs regs;
GetCPUID(0x80000000, ®s);
if(regs.EAX >= 0x800000006)
{ /* cache information available */
GetCPUID(0x80000006, ®s);
ECX6x ECX;
ECX.w = regs.ECX;
CacheSize = ECX.bits.CacheSize * 1024;
...
} /* cache information available */
EAX: L2 TLB parameters, 2M/4M pages 31 28 27 16 15 12 11 0 +--------+------------------------+--------+-------------------------+ |D assoc | D size |I assoc | I size | +--------+------------------------+--------+-------------------------+ | | +-----------------------------+ | 00 reserved 01 direct mapped 02..FE n-way mapping FF fully associative
typedef union { // 2M and 4M TLB parameters
struct {
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT InstCount:12; // 11..0
UINT InstAssoc:4; // 15..12
UINT DataCount:12; // 27..16
UINT DataAssoc:4; // 31..28
} AMD; // high order
UINT w;
} EAX6x;
EBX: L2 TLB parameters, 4K pages 31 28 27 16 15 12 11 0 +--------+------------------------+--------+-------------------------+ |D assoc | D size |I assoc | I size | +--------+------------------------+--------+-------------------------+ | | +-----------------------------+ | 00 reserved 01 direct mapped 02..FE n-way mapping FF fully associative
typedef union { // 4K TLB parameters
struct {
UINT Reserved:32; // 31..0
} Intel;
struct { // low order
UINT InstCount:12; // 11..0
UINT InstAssoc:4; // 15..12
UINT DataCount:12; // 27..16
UINT DataAssoc:4; // 31..28
} AMD; // high order
UINT w;
} EBX6x;
Intel:
ECX:
31 16 15 12 11 8 7 0
+------------------------------+--------+--------+----------------+
| Cache size in 1K units |L2 Assoc|########| CacheLineSize |
+------------------------------+--------+--------+----------------+
|
|
IDS_L2_ASSOCIATIVITY_00H "Disabled"
IDS_L2_ASSOCIATIVITY_01H "Direct mapped"
IDS_L2_ASSOCIATIVITY_02H "2-way associative"
IDS_L2_ASSOCIATIVITY_04H "4-way associative"
IDS_L2_ASSOCIATIVITY_06H "8-way associative"
IDS_L2_ASSOCIATIVITY_08H "16-way associative"
IDS_L2_ASSOCIATIVITY_0FH "Fully associative"
AMD:
typedef union {
struct { // low order
UINT LineSize:8; // 7..0
UINT Reserved1:4; // 11..8
UINT Associativity:4; // 15..12
UINT CacheSize:16; // 31..16
} Intel; // high order
struct { // low order
UINT LineSize:8; // 7..0
UINT LinesPerTag:4; // 11.8
UINT Associativity:4; // 15..12
UINT CacheSize:16; // 31..16
} AMD; // high order
UINT w;
} ECX6x;
All fields are reserved
This page is not displayed in release builds if GetCPUID(0x80000000).EAX < 0x800000007.
Intel: EAX: Reserved EBX: Reserved ECX: Reserved EDX: Reserved AMD: EAX: Reserved EBX: Reserved ECX: Reserved 31 9 8 7 6 5 4 3 2 1 0 +----------------------------------------------+--+----+--+--+--+--+--+--+ |##############################################|TI|####|ST|TM|TT|VI|FI|TS| +----------------------------------------------+--+----+--+--+--+--+--+--+ TI - TSC Invariant ST - Software Thermal Control TM - Harware Thermal Control TT - ThermaTrip supported VI - Voltage ID supported FI - Frequency ID supported TS - Temperature Sensor
typedef union {
struct { // low order
UINT TS:1; // 0
UINT FID:1; // 1
UINT VID:1; // 2
UINT TTP:1; // 3
UINT TM:1; // 4
UINT STC:1; // 5
UINT Reserved1:2; // 7..6
UINT TSCInvariant:1; // 8
UINT Reserved2:23; // 31..9
} AMD; // high order
UINT w;
} EDX7x;
This page is not displayed in release mode builds if GetCPUID(0x8000000).EAX < 0x80000008.
EAX:31 16 15 8 7 0 +------------------------------+-----------------+----------------+ |##############################|VirtualMemoryBits|PhysicalMemoryBi| +------------------------------+-----------------+----------------+EBX: ReservedECX: ReservedEDX: Reservedtypedef union { struct { // low order UINT PhysicalAddressBits:8; // 7..0 UINT VirtualAddressBits:8; // 15..8 UINT Reserved:16; // 31..16 } bits; // high order UINT w; } EAX8x;Useful Techniques
Note that if VirtualMemoryBits or PhysicalMemoryBits were to be 64, the actual memory size cannot be computed correctly because of overflow. For example
CPUregs regs; GetCPUID(0x8000008, ®s);
ULONGLONG MemorySize = 1 << EAX.PhysicalAddressBits;
will give an incorrect result when EAX.PhysicalAddressBits == 64. You will need to deal with this in a manner appropriate to your application.
CString s; const static ULONGLONG kilo = 1024; const static ULONGLONG mega = kilo * 1024; const static ULONGLONG giga = mega * 1024; const static ULONGLONG tera = giga * 1024; const static ULONGLONG peta = tera * 1024; const static ULONGLONG exa = peta * 1024;
ULONGLONG AddressMax = ((LONGLONG)1) << AddressBits;
if(AddressBits == 64)
s.Format(_T("%I64dEB"), ((((LONGLONG)1) << 63) / exa) * 2);
else
if(AddressMax / exa > 0)
s.Format(_T("%I64d EB"), AddressMax / exa);
else
if(AddressMax / peta > 0)
s.Format(_T("%I64d PB"), AddressMax / peta);
else
if(AddressMax / tera > 0)
s.Format(_T("%I64d TB"), AddressMax / tera);
else
if(AddressMax / giga > 0)
s.Format(_T("%I64d GB"), AddressMax / giga);
else
if(AddressMax / mega > 0)
s.Format(_T("%I64d MB"), AddressMax / mega);
else
if(AddressMax / kilo > 0)
s.Format(_T("%I64d KB"), AddressMax / kilo);
else
s.Format(_T("%I64d B"), AddressMax);
(No screen shot available)
This page is not displayed in release mode if CPUID(0x80000001):ECX.SVM is 0.
EAX: 31 8 7 0 +------------------------------------------------+----------------+ |################################################| SVM revision | +------------------------------------------------+----------------+ EBX: NASID ECX: Reserved EDX: Reserved
typedef union {
struct { // low order
UINT SVMRev:8; // 7..0
UINT Reserved:24; // 31..8
} AMD; // high order
UINT w;
} EAX10x;
The .cpuid files are in XML format. Note that the parser used to recognize these is not a full XML parser and therefore this format is fairly rigid. The filename is synthesized from the values in GetCPUID(0x80000002)..GetCPUID(0x80000004). This file was named "Dual Core AMD Opteron(tm) Processor 265.cpuid". In the interest of conciseness, a few elements which are all 0 values are elided.
<?xml version "1.0"?> <CPUID:id name="Dual Core AMD Opteron(tm) Processor 265"/> <CPUID:block> <CPUID:CPUID EAX="0x0"> <CPUID:EAX value="0x00000001" /> <CPUID:EBX value="0x68747541" /> <CPUID:ECX value="0x444d4163" /> <CPUID:EDX value="0x69746e65" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x1"> <CPUID:EAX value="0x00020f12" /> <CPUID:EBX value="0x00020800" /> <CPUID:ECX value="0x00000001" /> <CPUID:EDX value="0x178bfbff" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000000"> <CPUID:EAX value="0x80000018" /> <CPUID:EBX value="0x68747541" /> <CPUID:ECX value="0x444d4163" /> <CPUID:EDX value="0x69746e65" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000001"> <CPUID:EAX value="0x00020f12" /> <CPUID:EBX value="0x00000c04" /> <CPUID:ECX value="0x00000003" /> <CPUID:EDX value="0xe3d3fbff" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000002"> <CPUID:EAX value="0x6c617544" /> <CPUID:EBX value="0x726f4320" /> <CPUID:ECX value="0x4d412065" /> <CPUID:EDX value="0x704f2044" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000003"> <CPUID:EAX value="0x6f726574" /> <CPUID:EBX value="0x6d74286e" /> <CPUID:ECX value="0x72502029" /> <CPUID:EDX value="0x7365636f" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000004"> <CPUID:EAX value="0x20726f73" /> <CPUID:EBX value="0x00353632" /> <CPUID:ECX value="0x00000000" /> <CPUID:EDX value="0x00000000" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000005"> <CPUID:EAX value="0xff08ff08" /> <CPUID:EBX value="0xff20ff20" /> <CPUID:ECX value="0x40020140" /> <CPUID:EDX value="0x40020140" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000006"> <CPUID:EAX value="0x00000000" /> <CPUID:EBX value="0x42004200" /> <CPUID:ECX value="0x04008140" /> <CPUID:EDX value="0x00000000" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000007"> <CPUID:EAX value="0x00000000" /> <CPUID:EBX value="0x00000000" /> <CPUID:ECX value="0x00000000" /> <CPUID:EDX value="0x0000000f" /> </CPUID:CPUID> <CPUID:CPUID EAX="0x80000008"> <CPUID:EAX value="0x00003028" /> <CPUID:EBX value="0x00000000" /> <CPUID:ECX value="0x00000001" /> <CPUID:EDX value="0x00000000" /> </CPUID:CPUID> </CPUID:block>
The filename "Dual Core AMD Opteron(tm) Processor 265.cpuid". is synthesized from the indicated string, which is shown below
<CPUID:CPUID EAX="0x80000002"> <CPUID:EAX value="0x6c617544" /> 'lauD' <CPUID:EBX value="0x726f4320" /> 'roC ' <CPUID:ECX value="0x4d412065" /> 'MA e' <CPUID:EDX value="0x704f2044" /> 'pO D' </CPUID:CPUID> <CPUID:CPUID EAX="0x80000003"> <CPUID:EAX value="0x6f726574" /> 'oret' <CPUID:EBX value="0x6d74286e" /> 'mt(n' <CPUID:ECX value="0x72502029" /> 'rP )' <CPUID:EDX value="0x7365636f" /> 'seco' </CPUID:CPUID> <CPUID:CPUID EAX="0x80000004"> <CPUID:EAX value="0x20726f73" /> ' ros' <CPUID:EBX value="0x00353632" /> '\0562' <CPUID:ECX value="0x00000000" /> '\0\0\0\0' <CPUID:EDX value="0x00000000" /> '\0\0\0\0'
![[Dividing Line Image]](div.gif){kind=small}
The views expressed in these essays are those of the author, and in no way represent, nor are they endorsed by, Microsoft.